1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a structure of scribed lines which are formed in a semiconductor substrate and provided for separating chips.
The present application is based on Japanese Patent Application No. Hei. 11-147211, which is incorporated herein by reference.
2. Description of the Related Art
In forming semiconductor devices, a plurality of integrated circuits and the like are generally formed simultaneously on a single semiconductor substrate, and are finally separated along scribed lines. The scribed line is a linear region having a predetermined width where the processing of separation grooves for chip separation is allowed. Conventionally, a number of techniques for forming semiconductor elements and the like for testing, on the scribed lines have been proposed. For example, Japanese Patent Application Laid-Open No. Sho. 57-113241 discloses a technique whereby semiconductor elements for measuring the basic characteristics of circuits or manufacturing parameters are formed on the scribed line or its vicinity so as to make effective use of the scribe regions. For example, Japanese Patent Application Laid-Open No. Sho. 59-14663 discloses a technique whereby areas of monitoring semiconductor elements are made large, and the monitoring semiconductor elements are formed along the scribed lines for the purpose of enhancing the accuracy of detection of faulty withstand pressure ascribable to crystal defects. For example, in Examined Japanese Patent Publication No. Hei. 7-120696, an embodiment shown in FIG. 2 shows the formation of a monitor pattern on a scribed line to prevent the degree of integration from declining.
However, with the conventionally proposed techniques described above, the portion of the scribed line where the elements are formed and the remaining portion are formed with a fixed uniform width. In order to secure a large effective area for the chip and to reduce the size of the actual chips that are cut out, the width of the scribed lines is preferably narrow. However, if an attempt is made to secure a fixed region for the testing semiconductor element within the scribed line, the reduction of its width is limited by the testing semiconductor element, and therefore there is a limit.